1. Field
Embodiments relate to a semiconductor device with a vertical channel transistor and a method of operating the same.
2. Description of the Related Art
To increase an integration of semiconductor device, efforts for reducing a line width of pattern of semiconductor device have been performed. However, technologies of forming a fine pattern for a next generation semiconductor device require a new and high cost exposure technology.
As an alternative, methods of reducing an occupation area of unit cell constituting a semiconductor device have been studied. For example, a vertical channel transistor including a source electrode and a drain electrode formed on an upper portion and a lower portion of a channel region, respectively, is actively being studied. In the case of the vertical channel transistor, since separate areas for source and drain electrodes are not needed, an integration of semiconductor device may be greatly increased compared to a conventional planar MOSFET (metal-oxide semiconductor field-effect transistor) in which source and drain electrodes are disposed on both sides of the channel region. When the vertical channel transistor is manufactured using the next generation fine pattern formation technology, an integration of semiconductor device, including the vertical channel transistor may be increased. However, in the case of the conventional vertical channel transistor, technical difficulties different from a conventional two dimensional transistor exist, which pose challenges to mass-production of the semiconductor device.